The BlueGene/Q processors that will power the 20 petaflops Sequoia supercomputer being built by IBM for Lawrence Livermore National Labs will be the first commercial processors to include hardware support for transactional memory. Transactional memory could prove to be a versatile solution to many of the issues that currently make highly scalable parallel programming a difficult task.
Apparently the memory supports transactional code blocks in atomic fashion using processes similar to "load-link/store-conditional" (PowerPC) and "compare and swap" (x86), and it's all done using FPGAs. Pretty nifty.